Notes on Phase-Locked Loop (PLL) design

When I was an Electrical Engineering (EE) undergrad, I was very curious and interested about Phase-Locked Loops (PLLs). It all started when I interned for one summer at a high-tech start-up and one of the many talented engineers who worked there gave me such a clear, concise and intuitive explanation about it, that I sort of fell in love with the topic.

Later in my studies, I would find PLL’s in a couple of courses I took, but I never had much time to explore them in detail. After graduation, I occasionally talked to a few friends working in the micro-electronics industry and I got to know a bit more about the challenges and difficulties of analog and digital PLL design.

[ image courtesy of microblog ]

To all of you who are still working in EE, this post on PLL design which I found on Nick’s microblog will likely be of great interest:

I am coming to the realization that the PLL is one of the most under-appreciated components used in almost all aspects of electrical engineering. In many PLL applications, such as clock generation, the ratio of the output frequency to driving frequency is below ten, but a well designed PLL can push this ratio to several orders of magnitude. Finally, very special regard must be held for designers of very low frequency PLLs since keeping track of things for tens of milliseconds or more is very difficult in the analog domain. This is not to discredit designers of very fast (>500MHz) PLLs where the high frequencies tend to bring out non-ideal effects.

First, here is a guide from Freescale Semi. that outlines the design of PLLs through a control theory approach based in the s-domain. Next, here is an application note written by Bob Pease in 1979 that describes some non-standard uses for PLLs as well as low (~1-10kHz) frequency design. Finally, here is report from MOSIS outlining a physical implementation of a given PLL design. (MOSIS tends to publish the projects that it funds internally for universities.)

I don’t quite agree with Nick when he says that PLLs are under-appreciated. The people I got to talk to all had the highest respect for PLL design, and how crucial PLLs are. I quite enjoyed Freescale’s guide, the one which uses a classical control-theoretic approach.

Tags: Electronics, Phase-Locked Loops